1. Technical Field
The present disclosure relates to digital arithmetic circuits in general, and, in particular, to fused multiply-adder circuits.
2. Description of Related Art
The Institute of Electrical and Electronics Engineers (IEEE) standard for floating-point arithmetic defines specific formats for representing floating-point numbers. According to the IEEE standard, a floating-point number includes a sign bit, an exponent, and a fraction. The value of a floating-point number X is represented by:X=(−1)Xs*(1.Xf)*2(Xe-bias) where Xs is a sign bit, 1.Xf is intended to represent the binary number created by prefixing Xf with an implicit leading 1 and a binary point, and Xe is the unsigned binary exponent. If Xe=0, X is considered a denormalized number, and its value is instead represented by:X=(−1)Xs*(0.Xf)*2(I-bias) 
The IEEE standard also defines floating-point numbers in multiple levels of precisions. For example, a single-precision floating-point number has an 8-bit exponent and a 23-bit fraction, a double-precision floating-point number has an 11-bit exponent and a 52-bit fraction, and a quadruple-precision floating-point number has a 15-bit exponent and a 112-bit fraction.
Modern computer processors typically include a floating-point unit to perform mathematical operations on floating-point numbers according to the IEEE standard. One important floating-point instruction is the multiply-add instruction that implements the operationT=A*B+C in one step with only one rounding error (instead of two that would result from executing a multiply instruction followed by an add instruction). Two different approaches have been used for implementing the fused multiply-add instruction to support multiple precisions of floating-point numbers. The first approach uses separate data paths for each number precision, so instructions using single- and double-precision numbers, for example, can be executed at the same time, but at the expense of a larger chip area. The second approach uses only one data path capable of handling both single- and double-precision numbers, but only half the operand bandwidth is utilized when handling single-precision numbers.
Consequently, it would be desirable to provide an improved fused multiply-adder for performing multiply-add instructions.